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Mon 20 Jan 2020 11:45 - 12:07 at Maurepas - Automated verification and SAT solving Chair(s): Ori Lahav

Verification of modern microprocessors is a complex task that requires a substantial allocation of resources. Despite significant progress in formal verification, the goal of complete verification of an industrial design has not been achieved. In this paper, we describe a current contribution of formal methods to the validation of modern x86 microprocessors at Centaur Technology. We focus on proving correctness of instruction implementations, which includes the decoding of an instruction, its translation into a sequence of micro-operations, any subsequent execution of traps to microcode ROM, and the implementation of these micro-operations in execution units. All these tasks are performed within one verification framework, which includes a theorem prover, a verified symbolic simulator, and SAT solvers. We describe the work of defining the needed formal models for both the architecture and micro-architecture in this framework, as well as tools for decomposing the requisite properties into smaller lemmas which can be automatically checked. We additionally cover the advantages and limitations of our approach. To our knowledge, there are no similar results in the verification of implementations of an x86 microprocessor.

Mon 20 Jan

Displayed time zone: Saskatchewan, Central America change

11:45 - 12:30
Automated verification and SAT solvingCPP at Maurepas
Chair(s): Ori Lahav Tel Aviv University
Verifying x86 Instruction Implementations
Shilpi Goel Centaur Technology, Inc., Anna Slobodova Centaur Technology, Inc., Rob Sumners Centaur Technology, Inc., Sol Swords Centaur Technology, Inc.
DOI Pre-print File Attached
Frying the Egg, Roasting The Chicken: Unit Deletions in DRAT Proofs
DOI Pre-print Media Attached